Design & Test of SoC for EMC Workshop - Call for Participation

CALL FOR PARTICIPATION

Workshop Overview -- Preliminary Program -- Committees

Workshop Overview

This workshop is an embedded activity in the Technical Program of the EMC Europe2006 Conference (www.emceurope2006.org), to be held in Barcelona, September 4th - 8th, 2006.

Recent explosion in the portable electronics market combined with increasingly hostile electromagnetic environment have intensified the need to include noise-immune design and test methods in applicable low-power integrated circuits, in particular for complex microprocessor-based SoCs.

This workshop focuses on the design of embedded systems intended to operate in harsh environments, such as the EM one. The main themes addressed are:

HW/SW-based fault-handling mechanisms in microprocessors.
Testing for the signal integrity of modern complex integrated circuits (ICs), which present an increasing number of transistors in a large silicon area.
New approaches to mitigate the main sources of EM emission, which causes embedded IC functional blocks and/or interconnects to radiate undesired noise.
EMC specifications for IC test: standards, procedures, measurement and instrumentation requirements.

Preliminary Program

top

Foreseen Timetable:

Tuesday, Sep 5th, 2006

8:20 – 10:45
break (20 min)
11:15 – 13:00

Total time: 4 hours and 30 min.

Time allocated (min)	Technical Program
15	Opening Address – F. Vargas, V. Champac
50	Invited Talk: SoC Susceptibility to EMI. Franco Fiori – Politecnico di Torino, Italy.
80	Oral presentations: Emission and Susceptibility Issues in Systems-on-chip for EMC. Etienne Sicard – INSA / Toulouse, France. Modeling the Effectiveness of On-Chip Decoupling Capacitors for PSN and EMI Reduction. Josep Rius – UPC, Spain. Hybrid Solutions for Leveraging SoC Robustness in EMI-Exposed Environments. Fabian Vargas – PUCRS, Brazil. Testing for Complex ICs Signal Integrity. Victor Champac – INAOE, Mexico.
20	Coffee-Break
90	*Panel:** SoC Design & Test Roadmap for EM Compatibility and Collaborative Perspectives. Panelists: Etienne Sicard, INSA - France Fabian Vargas, PUCRS - Brazil Fernando Hernández, ORT / URSEC - Uruguay Franco Fiori, Politecnico di Torino - Italy João Paulo Teixeira - INESC/ID, Portugal Josep Rius, UPC - Spain
15	Closing Remarks
* To be published by IEEE Design & Test of Computers Magazine

Committees

top

General Chairs
Fabian Vargas
Catholic University – PUCRS
Electrical Engineering Dept.
Brazil
vargas@computer.org

Victor Champac, INAOE - Mexico
INAOE
Mexico
champac@inaoep.mx

Organizing Committee

Daniel Lupi, INTI - Argentina
Eduardo Todt, PUCRS - Brazil
Fernando Hernández, ORT / URSEC - Uruguay
Franco Fiori, Politec. di Torino - Italy
João Paulo Teixeira, INESC-ID / IST - Portugal
Jorge Salcedo, Texas Instruments - USA
José Luis Huertas, IMSE / CNM - Spain
Josep Rius, UPC - Spain
Juan José Rodríguez Andina, Univ. of Vigo - Spain
Kaushik Roy, Purdue Univ. - USA
Yervant Zorian, Virage Logic - USA

EMC Europe2006 Liaison

Ferran Silva, UPC - Spain

For more information, visit us on the web at: http://www.emceurope2006.org/

The Design & Test of Systems-on-Chip for EMC Workshop (EMC Europe2006) is in-concurrence with the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).